The field of the invention is that of logic circuits with embedded DRAM arrays.
In the currently active field of integrated circuits having DRAM arrays embedded in a chip that is primarily logic, the art has tried many approaches to reconcile the different process steps for the logic transistors and processes and the DRAM transistors and processes.
Both logic and DRAM have been refined over several generations, with the result that the process steps for the two types of circuits have diverged. Executing all the steps of the two processes in parallel would preserve the refinements of both approaches, but at commercially impractical cost. In the field of embedded DRAMS the current challenge is to devise an integrated process that will lower costs, while still preserving the advantages of logic and DRAM circuits to the maximum extent possible.
The invention relates to an embedded DRAM process that provides logic transistors with source/drain regions isolated from the substrate for reduced capacitance and simultaneously uses steps in that process to provide a buried strap in the memory array to connect the capacitors in the memory cells with their pass transistors.